Will Bug Free Chips Be A Reality Soon
Two years ago, Application Response Measurement (ARM) investigated the way in which its teams undertook hardware design. Tools developed for cloud computing were used for investigation. In order to find patterns, now ARM examines every result from the thousands of tests and simulations that run on a daily basis.
Bryan Dickman, director of engineering analytics in ARM’s technology services group, had said in:
“RTL verification generates a lot of data. It’s becoming a big-data problem. We do a lot of analytics around bugs. We drill into bugs by methodology and areas of the design: what methodologies find bugs and when. It is interesting to see how you are finding bugs against the amount of verification you are running. You can start asking questions like ‘I have been running lots of cycles, but no bugs were discovered: were they dumb cycles?”
At the moment, emphasis has been on building visualization tools that can help engineers to analyze the patterns. Building the tools that can learn from the data has been planned as the next step. Dickman elaborated:
“We are looking at how we can take machine-learning algorithms and apply them to the data, then design predictive workflows that improve productivity.”
Growth of Machine Learning technique:
Machine Learning (ML) has been a growing phenomenon across the Electronic Design Automation (EDA) world. Today more than 20% of papers at the 2017 Design Automation Conference (DAC) are dealing (or have dealt) with ML techniques. At the moment, the biggest problems in this regard are uneven distribution of applications and access to data.
Ting Ku, senior director of engineering at nVidia, talked about tuning ML techniques to address the problems associated with them. He said:
“When people talk about ML, most think it’s neural network-related. But the data doesn’t have to be modelled by a neural network.”
Today, there have been attempts by organizations to combine domain knowledge with various forms of ML in their tools, in order to tune the parameters used to compile Field-Programmable Gate Array (FPGA) designs for area and performance.
Plunify co-founder Kirvy Teo said:
“The nature of ML in this area is different from the things we see at Google. Neural networks work very well for lots of data points, but we are dealing with thousands of data points, rather than billions.”
ML techniques ranging from simple regression algorithms that fit a curve to a collection of data points can be applied by EDA tool developers, to more advanced techniques. Such techniques support vector machines with efficient image recognition ability. Now these machines are set to be more advanced with learning.
Different companies are launching different ML-oriented initiatives. They created their own toolkits of techniques and use them in their tools. Many of such toolkits analyze models of low-level behavior of the cell libraries are used in Integrated Circuit (IC) design on advanced processes. As these processes go on, statistical variation at the nanometer scale affects the performance of the device.
There is no guarantee of effects of temperature and voltage being always linear. Hence, there is need to characterize the cells at all possible operating points. The tools analyze the interaction between variables in existing libraries. They build models to predict the parameters for a subset of simulations that will create effective library.
Amit Gupta, CEO of Solido that is working on this initiative explains:
“We have been focused on ML for variation-aware design for the past seven years and are expanding that into other areas. The first area is characterisation, but we are getting demand from customers to expand into other areas within EDA.”
ML achievements & verification issues:
Using ML requires process verification across multiple process corners. Problem faced by physical-verification teams is the number of combinations of transistor speeds, temperature and voltage. Regarding productivity, ML brings ten times more improvement in productivity.
RTL verification teams have achieved success with ML methods with regards to elimination of verification cycles that concern ARM’s designers.
Harry Foster, chief scientist at Mentor, says:
“Can I minimise the number of tests and still achieve a reasonable level of coverage? There are papers on that and it is a technique now being applied in the industry.”
One area where RTL verification teams have achieved success with ML methods is in eliminating some verification cycles concerning ARM’s designers. These cycles are seen as time wastage by many.
ML has also achieved an improvement in Yield analysis area that predicts the types of geometry in a design that is dense enough to lead to lithographic or other process failures and dud chips.
A key purpose of ML is to make it easier to build simplified models of complex interactions that defy rule-based design methods.
Nowadays models are generated automatically from electromagnetic measurements and simulations. These models are helpful when it comes to organizing the devices and I/O pins on multi-chip modules. Organizing the devices ensures that signals do not suffer from Instruction Register (IR) drop or crosstalk.
Mr. Foster said:
“Where ML doesn’t work well is where you have to guarantee finding something, like manufacturing test. With verification, I can get away with less than 100% coverage, because my intent is mitigating risk. I can’t with manufacturing test, because it leads to returns”.
Industry plans to reuse ML across multiple projects. Issues that slow down the adoption of ML and data mining in RTL verification.
Mr. Foster proceeded:
“The issue with [RTL] verification is that although people say we have lots of data, the reality is we don’t. If I’m starting a project, I have no data. How can we be successful in applying ML techniques if our data is limited? It can’t be based just on pure data mining; it has to incorporate some domain knowledge.”
Experts believe that lack of data being reflected in physical implementation. Hence, data mining is needed to look at repetitive tasks and automate them.
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